LDMOS and CMOS integrated circuit and method of making

ABSTRACT

An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second well having a dopant concentration equal to the first dopant concentration that includes a first conductivity high-voltage transistor. In addition, the IC has a third well having a second dopant concentration of an opposite type than the first well that includes a first conductivity low-voltage transistor. The first conductivity low-voltage transistor and the second conductivity low-voltage transistor are created without a threshold voltage (V t ) implant.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor integrated circuitdevices, processes for making those devices and systems utilizing thosedevices. More specifically, the invention relates to a combined LDMOSand CMOS integrated circuit.

BACKGROUND OF THE INVENTION

CMOS (complimentary metal oxide semiconductors) integrated circuits arefinding increased use in electronic applications such as printers. Thereare at least two important classes of transistor integrated circuits,low-voltage circuits in which the operating voltages are less than aboutsix volts and high-voltage circuits in which the operating voltages areabove about thirty volts. Moreover, the important difference in the twoclasses of transistors is that the high-voltage transistors require thechannel region between the source and drain of the high-voltagetransistor to be able to withstand a higher induced electric fieldwithout experiencing avalanche breakdown (punch through). As aconsequence, the two classes of transistors have generally involveddifferences in structure, as well as differences in parameters. Suchdifferences have dictated enough differences in processing that eachclass typically had been formed on its own separate integrated circuit(IC) rather than combined with the other class on a single IC.

Integrated circuit manufacturers have now incorporated high-voltagepower MOSFET devices, such as a lateral double diffused MOS transistor(LDMOS) with CMOS control circuits to allow for versatility of designand increased reliability. This incorporation requires that relativelylow-voltage CMOS logic circuits operate on the same die as a relativelyhigh-voltage power transistor. While the incorporation has reduced totalsystem costs, the fabrication of the combined CMOS and LDMOS transistorsis still complex and expensive. In competitive consumer markets such aswith printers and photo plotters, costs must continually be reduced inorder to stay competitive and profitable. Further, the consumers expectincreasingly reliable products because the cost of repair to thecustomers is often times higher than the cost of replacing the product.Therefore, to increase reliability and reduce costs, improvements arerequired in the manufacturing of integrated circuits that combine CMOSand LDMOS transistors.

SUMMARY

An integrated circuit (IC) is formed on a substrate. The IC has a firstwell having a first dopant concentration that includes a secondconductivity low-voltage transistor. The IC also has a second wellhaving a dopant concentration equal to the first dopant concentrationthat includes a first conductivity high-voltage transistor. In addition,the IC has a third well having a second dopant concentration of anopposite type than the first well that includes a first conductivitylow-voltage transistor. The first conductivity low-voltage transistorand the second conductivity low-voltage transistor are created without athreshold voltage (V_(t)) implant.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exemplary cross-section of an integrated circuit thatcombines CMOS transistors with an LDMOS transistor.

FIG. 2 is an exemplary block diagram of a circuit using the combinedCMOS and LDMOS transistors embodied by the invention.

FIG. 3A is an exemplary flow chart of a process embodying the invention.

FIG. 3B is an exemplary flow chart for a process that incorporates theinvention.

FIGS. 4A and 4B is an exemplary flow chart of a semiconductor processembodying the invention.

FIG. 5A-5M are exemplary cross-sectional views of semiconductorprocessing steps used in FIGS. 4A and 4B.

FIG. 6 is an exemplary printhead integrated circuit made by a processthat embodies the invention.

FIG. 7 is an exemplary recording cartridge that includes the exemplaryprinthead of FIG. 6.

FIG. 8 is an exemplary recording device that includes the exemplaryfluid cartridge of FIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED AND ALTERNATE EMBODIMENTS

In conventional IC processes, a threshold voltage (V_(t)) adjustingimplant step is used as a control knob to adjust low-voltage CMOStransistor gate threshold voltages. The same V_(t) implant is applied toboth the NMOS and PMOS low-voltage transistors. The high-voltage LDMOStransistor is masked to prevent the V_(t) implant in order to keep theon-resistance of the LDMOS transistor low. A V_(t) protection mask forthe LDMOS is used in conventional IC processes. For example, with a Psubstrate, the low-voltage CMOS N-Well has a higher doping concentrationthan the high-voltage LDMOS N-Well. The lower doping concentration forthe high-voltage N-Well is required to maintain a high breakdown voltage(punch-through) and a low leakage current to the substrate. Due to theseconstraints, the low-voltage and the high-voltage N-Wells have differentdopant concentrations levels.

The present invention is directed to a process for providing bothhigh-voltage and low-voltage transistor devices in a common substratethat eliminates several process steps used in conventional processes.The invention simplifies and reduces the cost of conventional processesby redesigning the Well dopant concentrations and foregoing the V_(t)adjust implant process steps while maintaining substantially the samethreshold voltages and breakdown voltages of the conventional processes.Thus, well doping alone is used to control the V_(t) of the NMOS andPMOS low-voltage transistors. For example, in one embodiment P-Welldoping is used to control NMOS V_(tn) and N-Well doping is used tocontrol PMOS V_(tp), separately, without using the V_(t) adjust implant.This simplified process not only eliminates the V_(t) implant step butalso allows use of a single N-Well dopant concentration for bothlow-voltage PMOS and high-voltage LDMOS transistors. The improvedprocess eliminates at least two photo mask layers (one N-Well mask andthe V_(t) block mask), two implants (one N-Well implant and the V_(t)adjust implant) and one furnace operation (channel oxidation prior tothe V_(t) implant). Significant process cost reduction and cycle time isachieved. The changes in process flow between conventional and newprocesses occurs during the early stage of the new process, thusallowing the remaining steps of the new process to remain the same aswith the conventional process.

It should be noted that the drawings are not true to scale. Moreover, inthe drawings, heavily doped regions (concentrations of impurities of atleast 1×10¹⁹ impurities/cm³) are designated by a plus sign (e.g., n⁺ orp⁺) and lightly doped regions (concentrations of no more than about5×10¹⁶ impurities/cm³) by a minus sign (e.g. p⁻ or n⁻).

The specific process to be described involves a p-type substrate as thebulk in which N-Wells are formed for use with the low-voltage PMOStransistor and the high-voltage LDMOS transistor. Alternatively, ann-type substrate can be used as the bulk and a separate P-Well formedtherein for use by low-voltage NMOS transistors.

Accordingly, the semiconductor devices of the present invention areapplicable to a broad range of semiconductor devices and can befabricated from a variety of semiconductor materials. The followingdescription discusses several presently preferred embodiments of thesemiconductor devices of the present invention as implemented in siliconsubstrates, since the majority of currently available semiconductordevices are fabricated in silicon substrates and the most commonlyencountered applications of the present invention will involve siliconsubstrates. Nevertheless, the present invention may also advantageouslybe employed in gallium arsenide, germanium, and other semiconductormaterials. Accordingly, the present invention is not intended to belimited to those devices fabricated in silicon semiconductor materials,but will include those devices fabricated in one or more of theavailable semiconductor materials available to those skilled in the art.

Moreover, while the present invention is illustrated by preferredembodiments directed to silicon semiconductor devices, it is notintended that these illustrations be a limitation on the scope orapplicability of the present invention. Further, while the illustrativeexamples use insulative gate control structures, it should be recognizedthat the insulated gate portions may be replaced with light activated orcurrent activated structure(s). Thus, it is not intended that thesemiconductor devices of the present invention be limited to thestructures illustrated. These structures are included to demonstrate theutility and application of the present invention to presently preferredembodiments.

Further, various parts of the semiconductor elements have not been drawnto scale. Certain dimensions have been exaggerated in relation to otherdimensions in order to provide a clearer illustration and understandingof the present invention. For the purposes of illustration the preferredembodiment of semiconductor devices of the present invention have beenshown to include specific P and N type regions, but it should be clearlyunderstood that the teachings herein are equally applicable tosemiconductor devices in which the conductivities of the various regionshave been reversed, for example, to provide the dual of the illustrateddevice. Enhancement and depletion mode structures may be similarlyinterchanged.

Further, although the embodiments illustrated herein are shown intwo-dimensional views with various regions having depth and width, itshould be clearly understood that these regions are illustrations ofonly a portion of a single cell of a device, which may include aplurality of such cells arranged in a three-dimensional structure.Accordingly, these regions will have three dimensions, including length,width, and depth, when fabricated on an actual device.

The term high-voltage denotes the voltages to which the drain of thedevice formed will be subjected; high-voltages, such as twelve andeighteen volts with transients greater than 40V usually require largerand deeper wells but with smaller (or lighter) dopant concentrations.Low-voltage devices are subjected to voltages generally less than 10volts, preferably less than 6V.

FIG. 1 is an exemplary cross-section of an integrated circuit thatcombines low-voltage CMOS transistors with a high-voltage LDMOStransistor. The integrated circuit includes a substrate 10, preferablysilicon, that contains a first region 20, preferably an N-doped well, asecond region 22, preferably an N-doped well, and a third region 24,preferably a P-doped well. The first region 20 includes a secondconductivity low-voltage transistor 26, preferably a PMOS type device.The third region 24 includes a first conductivity low-voltage transistor28, preferably an NMOS type device. The second region 22 includes afirst conductivity high-voltage transistor 30, preferably a lateral dualdiffusion MOS (LDMOS) device. The first region 20 is doped with apredetermined concentration of impurities chosen to determine thevoltage threshold of the second conductivity low-voltage transistor 26.Also, the predetermined concentration of impurities that is chosen alsosets the breakdown voltage of the first conductivity high-voltagetransistor 30 in the second region 22. The second region 22 receives thesame predetermined concentration of impurities as the first region 20.The predetermined concentration of impurities is chosen to take intoaccount that a threshold voltage (V_(t)) implant step will not beperformed on the second conductivity low-voltage transistor 26. Whenchoosing the predetermined concentration, the process designer must alsotake into account that the selected value determines the voltagebreakdown of the first conductivity high-voltage transistor. Forexample, in a conventional process, the first low-voltage andhigh-voltage N-Well region's doping concentration is approximately2.5×10¹² impurities/cm² at 160 Kev implant energy. Then in theconventional process, the first N-Well region 20 would receive anadditional dopant implant of approximately 8.5×10¹² impurities/cm² at160 Kev implant energy to compensate for the later V_(t) implant step.For the modified process, only a single doping implant concentration isdone for the first 20 and second 22 N-Well regions. The predeterminedconcentration for the modified process is adjusted to compensate for thelack of V_(t) implant to be 2.75×10¹² to 3.0×10¹² impurities/cm²,preferably 2.75×10¹² impurities/cm² at 160 Kev implant energy. Thispredetermined doping level is applied simultaneously to the first andsecond regions such that they receive essentially the same dopantconcentration. Because the invention removes the V_(t) implant step, theconventional process's additional dopant implant step is not required.This also saves a photolithography step required to mask the secondregion 22 during the conventional process's additional dopant implantstep. By keeping the impurity concentration low in both the first region20 and the second region 22, the breakdown voltage of the firstconductivity high-voltage transistor 30 is maintained. Preferably, thebreakdown voltage of the first conductivity high-voltage transistor 30is greater than 40 volts.

FIG. 2 is an exemplary block diagram of a circuit using the combinedCMOS and LDMOS transistors of the invention in a printing application.The second conductivity low-voltage transistor 26 in the first region 20has its source connected to a low-voltage supply 32, preferably about 5volts or less. The first conductivity low-voltage transistor 28 in thethird region 24 has its source connected to ground 36. The drains of thefirst and second conductivity low-voltage transistors are connected andcoupled to the gate of the first conductivity high-voltage transistor 30that resides in the second region 22. The source of the firstconductivity high-voltage transistor 30 is connected to ground 36. Thedrain of the first conductivity high-voltage transistor 30 is coupled toan energy dissipation element 40 that is further coupled to ahigh-voltage supply 34, preferably greater than 40 Volts. The first,second and third regions reside in substrate 10 of the integratedcircuit. Other control circuitry 21 on the integrated circuit or signalsexternal to the integrated circuit are connected to the gates of thefirst and second conductivity low-voltage transistors to control theirswitching which in turn controls the on-off state of the firstconductivity high-voltage transistor 30 which further controls currentfrom the high-voltage supply 34 to the energy dissipation element 40,preferably a thin film resistor used to eject fluid.

FIG. 3A is an exemplary flow chart of a process for creating anintegrated circuit with a second conductivity low-voltage transistor ina first region, a first conductivity high-voltage transistor in a secondregion, and a first conductivity low-voltage transistor in a thirdregion. In block 50 the first step is to create a defined deposition ofa first dielectric layer to expose a first well for the first region anda second well for the second region. In block 52, the first well and thesecond well are prepared for creating transistors without using avoltage threshold step. This step is performed by selectively doping thefirst and second well with essentially the same concentration ofimpurities such that the desired first conductivity low-voltagetransistor threshold voltage is met while still maintaining thebreakdown voltage requirement of the first conductivity high-voltagetransistor, then selectively doping the third region with a seconddopant concentration to control the threshold voltage of the firstconductivity low-voltage transistor. By selectively choosing the dopantlevels the conventional step of applying a threshold voltage adjustmentimplant to the first and second conductivity low-voltage transistors isexcluded. After the preparation of the regions/wells for creatingtransistors, the first and second regions/wells have substantially thesame dopant concentration of impurities. After the first, second andthird regions/wells are prepared, in step 54, thin-film layers areapplied and patterned on the regions to define gate areas of the desiredtransistors.

FIG. 3B is an exemplary flow chart describing the process of step 52 ofFIG. 3A which incorporates the invention. In step 100, the first andthird wells are doped with a first dopant concentration to control andset the threshold voltage (V_(t)) of the first polarity low-voltagetransistor. Then in step 102, the second well is doped with a seconddopant concentration to control and set the threshold voltage of thesecond polarity low-voltage transistor. Finally, in step 104, because ofthe chosen dopant concentrations used in steps 100 and 102, thethreshold voltage adjust implant step of conventional processes is notperformed on the first and second polarity low-voltage transistors.

FIGS. 4A and 4B make up an exemplary flow chart of a modifiedsemiconductor process embodying the invention. FIGS. 5A through 5M arecross-sectional views of exemplary and some excluded process steps on asubstrate 10. The step 50 of FIG. 3A of creating a defined deposition ofa first dielectric layer 124 to expose a first region 20 and a secondregion 22, is illustrated in FIG. 5A. The first dielectric layer 124 canbe made of one or more conventional thin film dielectrics. An exemplaryfirst dielectric layer is made up of 200 Angstroms of SRO (stress reliefoxide) and 900 Angstroms of silicon nitride. The process step 52 of FIG.3A can be performed to provide the selective doping of the well regionswith essentially the following steps. As shown in FIG. 5B and in step 60of FIG. 4A, a first conductivity dopant of impurities 126 is implantedinto the first and second 20/22 regions. An exemplary N-Well implant is2.8 to 3.0×10¹² impurities/cm² of phosphorous at 160 keV of energy. Thenin step 62 and FIG. 5C, a first protective coating 132 is applied overthe first and second 20/22 regions. An exemplary first protectivecoating is field oxide (FOX). Then in step 64 and FIG. 5C, the firstconductivity dopant 126 is driven into the substrate by baking thesubstrate 10, such as at 1200° C. for 4 hours. Then in step 66, thefirst dielectric layer 124 is removed. Then in step 68 and FIG. 5D, adefined deposition of a second dielectric layer 136 is created in thesame location as the defined deposition of the first dielectric layer124, such as channel oxide. Then in step 70 and FIG. 5D, a secondconductivity dopant 138 is implanted in the substrate 10 as secondconductivity implant 134 and disposed under the defined deposition ofthe second dielectric layer 136. An exemplary second conductivity dopant138 is boron at a concentration of 9.8×10¹² impurities/cm² at an energyof 33 keV. Then in step 72 and FIG. 5E, the second conductivity implant134 is driven into the substrate 10 to form a driven second conductivityimplant 140, preferably by baking the substrate 10 at 1200° C. at 4hours. Then in step 74 and FIG. 5E, the first protective coating 132 andthe second dielectric layer 136 are removed, for example, by using anoxide strip. Then in step 76 and FIG. 5F, a patterned third dielectriclayer 146 is created over the surface of the substrate to expose thedrain and source of the first 28 and second 26 conductivity low-voltagetransistors and the first conductivity high-voltage transistor 30. Thethird dielectric layer 146 can be made of one or more dielectric layers.An exemplary third dielectric layer is made up of 200 Angstroms of SROand 900 Angstroms of silicon nitride. Then in step 78, a defineddeposition of a fourth dielectric layer 148 is created and disposed onthe drain and source of the first conductivity low-voltage transistor28. Then in step 80 and FIG. 5G, a second protective coating 150, forexample photoresist, is applied over the first 142 and second 144 wells.Then in step 82 and FIG. 5H, a second conductivity field dopant 152 isimplanted into the substrate and disposed under the drain and source ofthe first conductivity low-voltage transistor 28. An exemplaryconcentration of the second conductivity field dopant 152 is boron at aconcentration of 8.5×10¹² impurities/cm² at and energy of 120 keV. Thenin step 84, the second protective coating 150 is removed. Then in step86 and FIG. 51, a fifth dielectric layer 154, for example FOX, iscreated in areas of the substrate where the third dielectric layer 146is not located. Then in step 88, the patterned third dielectric layer146 is removed, for example with an oxide strip.

FIGS. 5J and 5K and steps 90 and 92 illustrate at least some of theprocess steps of a threshold voltage adjust implant that have beeneliminated by the invention that occur in conventional processes. InFIG. 5J, a third protective coating 180 such as photoresist is disposedand patterned on the substrate 10. The third protective coating 180 haspatterned opening to expose the transistor regions of the first well 142and the third well 143. In FIG. 5K, a second conductivity implant, athreshold voltage adjust 160, is implanted into the surface of thetransistor regions 162/164 that are exposed. An exemplary thresholdvoltage adjust implant is boron at a doping concentration of 2×10¹²impurities/cm² at an energy of 35 keV to limit its implantation to nearthe surface of the transistor.

In step 94 and FIG. 5L, a sixth dielectric layer 170 is created over thesurface of the substrate 10 to form a gate oxide, for example 200Angstroms of SiO₂. In step 96, a gate material 172 is deposited over thesixth dielectric layer 170, for example, 3600 Angstroms of polysilicondeposition. Optionally, the gate material 172 can be doped to increaseconductivity. Finally, in step 54 of FIG. 3A and FIG. 5M, the sixthdielectric layer 170 and the gate material 172 are patterned to definethe gate regions 175 of the first 26 and second 28 conductivitylow-voltage transistors and the gate region 176 of the firstconductivity high-voltage transistor 30.

FIG. 6 is an exemplary prospective view of an integrated circuit, afluid jet printhead 200, which embodies the invention. Disposed onsubstrate 110 is a stack of thin-film layers 232 that make up thecircuitry illustrated in FIG. 2. Disposed on the surface of theintegrated circuit is an orifice layer 282 that defines at least oneopening 290 for ejecting fluid. The opening(s) is fluidically coupled tothe energy dissipation element(s) 40 (not shown) of FIG. 2.

FIG. 7 is an exemplary recording cartridge 220 that incorporates thefluid jet printhead 200 of FIG. 6. The recording cartridge 220 has abody 218 that defines a fluid reservoir. The fluid reservoir isfluidically coupled to the openings 290 in the orifice layer 282 of thefluid jet printhead 200. The recording cartridge 220 has a pressureregulator 216, illustrated as a closed foam sponge to prevent the fluidwithin the reservoir from drooling out of the opening 290. The energydissipation elements 40 (see FIG. 2) in the fluid jet printhead 200 areconnected to contacts 214 using a flex circuit 212.

FIG. 8 is an exemplary recording device 240 that uses the recordingcartridge 220 of FIG. 7. The recording device 240 includes a medium tray250 for holding media. The recording device 240 has a first transportmechanism 252 to move a medium 256 from the medium tray 250 across afirst direction of the fluid jet printhead 200 on the recordingcartridge 220. The recording device 240 optionally has a secondtransport mechanism 254 that holds the recording cartridge 220 andtransports the recording cartridge 220 in a second direction, preferablyorthogonal to the first direction, across the medium 256.

1. An integrated circuit on a substrate, comprising: a first well havinga first dopant concentration and including a second conductivity typelow-voltage transistor; a second well having a dopant concentrationequal to the first dopant concentration and including a firstconductivity type high-voltage transistor; a third well having a seconddopant concentration of an opposite type than the first well andincluding a first conductivity type low-voltage transistor; and whereinthe first conductivity type low-voltage transistor and the secondconductivity type low-voltage transistor are created without a thresholdvoltage (V_(t)) implant.
 2. The integrated circuit of claim 1, whereinthe first conductivity type high-voltage transistor is a lateraldual-diffusion metal oxide semiconductor.
 3. The integrated circuit ofclaim 2, wherein the first conductivity type high-voltage transistor hasa breakdown voltage of greater than. 40 volts.
 4. The integrated circuitof claim 1, further comprising an energy dissipation element coupled tosaid first conductivity type high-voltage transistor.
 5. A fluid jetprinthead, comprising: the integrated circuit of claim 4; and an orificelayer defining an opening for ejecting fluid thermally coupled to saidenergy dissipation element, said orifice layer disposed on the surfaceof the integrated circuit.
 6. A recording cartridge, comprising: thefluid jet printhead of claim 5; a body defining a fluid reservoir, saidfluid reservoir fluidically coupled to the opening in said orifice layerof the fluid jet printhead; and a pressure regulator to control thepressure of the fluid reservoir within the body of the recordingcartridge.
 7. A recording device for placing fluid on a medium,comprising: the recording cartridge of claim 6; and a transportmechanism to move the recording cartridge in at least one direction withrespect to the medium.
 8. The integrated circuit of claim 1 wherein thefirst and second wells are an N-wells and wherein the third well is aP-well.
 9. The integrated circuit of claim 1 wherein the firstconductivity type high-voltage transistor is an n conductivity typehigh-voltage transistor. 10-17. (cancelled).